Wafer-level Tracking Versus Other Techniques

During its fabrication, a semiconductor wafer passes through hundreds of process steps, pieces of equipment and physical locations. The continuous challenge of any semiconductor manufacturer is to minimize the introduction of defects and reduce sources of process variation throughout an extremely complex process. A combination of approaches is used:

A small percentage of individual wafers is inspected at specific points in the fabrication process.

Additionally, individual process steps include their own monitoring tests.

Pinpoint observation can reveal specific problems at the lot level or process stage, but when it comes to achieving visibility of unknown and undetected defect or process margin mechanisms, such limited sampling approaches often are not adequate.

With Wafer Sleuth, the necessary visibility is possible through fab-wide individual wafer-level tracking with purposeful reordering of process sequence. Unique positional histories are recorded for all wafers throughout the entire fabrication process to resolve the most elusive sources of yield loss and process variation.

With shrinking geometries and greater circuit complexity, a higher proportion of yield loss mechanisms is margin related, defying detection by defect inspection techniques. A unique strength of Wafer Sleuth is the ability to identify previously unseen sources of yield loss due to variation in process margin, as well as those due to particles.

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